1. Technical Field
The present application relates generally to systems and methods for manufacturing integrated circuits, particularly to optical proximity correction of integrated circuit layouts.
2. Related Art
The manufacturing of integrated circuit (IC) devices usually includes one or more photolithography processes. Photolithography is a common process that involves forming a pattern on a semiconductor substrate. The pattern can then be used for selective removal of material from the wafer. In this way, a desired pattern can be formed on the wafer.
However, for a variety of reasons, the desired pattern is not always precisely formed on the substrate. For example, FIG. 1A shows an example of an IC layout 10 that is desired to be formed on a wafer using photolithography, and FIG. 1B shows the resulting formation 12 on the wafer. The resulting formation 12 differs somewhat from the desired IC layout 10 due to errors introduced during the photolithographic processes. Such variations can cause significant problems with the resulting device, such as failures due to shorts and undesirable variations in device operation characteristics.
In order to avoid such problems, correction processes are typically performed on the IC layout before the IC layout is transferred to a wafer. One common correction process is known as optical proximity correction (OPC). OPC processes are known processes for modifying an IC layout, such as IC layout 10, to produce a corrected IC layout, such as the corrected IC layout 14 shown in FIG. 2A. OPC processes involve making modifications to the IC layout based on predicted variations in the photolithography process so that the resulting structure will more closely resemble the desired layout. For example, FIG. 2B shows the result of using the corrected IC layout 14 in a photolithographic process to produce a structure 16. Compared to structure 12, the structure 16 more closely resembles the desired layout 10 because of the OPC processes used to make the corrected IC layout 14.
A problem with correction processes such as OPC is that the correction processes are very complex and time consuming. For example, OPC processes are generally iterative processes that involve multiple iterations of modifying shapes and predicting the result of the modified shapes with the goal of approaching the desired shape through the numerous modification iterations. Also, a typical IC layout is far more complex than the very simple IC layout 10 shown in FIG. 1A. For example, an IC design may include 50 million transistors, which may be formed using IC layouts containing more than a billion shapes. For this reason, OPC processes are often performed using powerful computer systems having multiple processors and large amounts of memory. However, performing a multiple-iteration OPC process on such a layout will still generally require several hundred CPU hours.
Sometimes it is necessary to make changes to the IC design after the OPC process has already been performed on the IC layouts. FIG. 3 shows a flowchart of a conventional process for generating an IC layout when changes are made to the IC design. At blocks 20-26, an IC layout is generated based on an initial IC layout. Between blocks 26 and 30, changes are made to the initial IC layout. Then, at blocks 30-36, a revised IC layout is generated based on the revised IC layout.
Initially, at block 20, a database is provided containing data representative of a first IC layout. Various techniques are known in the art for generating data representative of a mask layout, and so such techniques are not described herein. Next, at block 22, assist features are added to the first IC layout. Assist features are features that are added to the layout, but are not intended to be formed on the wafer. Assist features are used to avoid defects by helping to enhance optical resolution during the photolithography process. Next, at block 24, the entire first IC layout undergoes the OPC process. Finally, at block 26, a corrected version of the first IC layout is output for masking and further photolithographic processes.
When a change is made to the first IC layout, a second database is created at block 30 containing data representative of a second IC layout, which is the modified version of the first IC layout. At block 32, assist features are added to the second IC layout, at block 34 the OPC process is performed on the entire second IC layout, and at block 36 a corrected version of the second IC layout is output for masking and further photolithographic processes.
Thus, when a change is made to an IC layout, the process for producing the mask data is repeated for the new IC layout, including performing the OPC process again for the entire revised IC layout. Since the OPC process is very time consuming, this means that any change to the IC layout requires a very time-consuming process for generating a corresponding revised mask layout.
Thus, it is desirable to find new approaches for revising an IC mask whenever changes are made to an IC layout.